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1 of 38 rev: 101006 note: some revisions of this device may incor porate deviations from published specifications known as errata. multiple revisions of any device may be simultaneously available through various sales channel s. for information about device errata, click here: www.maxim-ic.com/errata . features ? 80c32-compatible 8051 pin and instruction set compatible four 8-bit i/o ports three 16-bit timer/counters 256 bytes scratchpad ram addresses 64kb rom and 64kb ram ? high-speed architecture 4 clocks/machine cycle (8032 = 12) dc to 33mhz (ds80c320) dc to 18mhz (ds80c323) single-cycle instruction in 121ns uses less power for equivalent work dual data pointer optional variable length movx to access fast/slow ram/peripherals ? high-integration controller includes: power-fail reset programmable watchdog timer early warning power-fail interrupt ? two full-duplex hardware serial ports ? 13 total interrupt sources with six external ? available in 40-pin dip, 44-pin plcc, and 44-pin tqfp the high-speed microcontroller users guide must be used in conjunction with this data sheet. download it at: www.maxim-ic.com/microcontrollers . data sheets contain pin descriptions, feature overviews, and electrical specifications, whereas the users guide contains detailed information about device features and operation. pin configurations ds80c320/ds80c323 high-speed/low-power microcontrollers www.maxim-ic.com top view downloaded from: http:///
ds80c320/ds80c323 high-speed/low-power microcontrollers 2 of 38 detailed description the ds80c320/ds80c323 are fast 80c31/80c32-compa tible microcontrollers. wasted clock and memory cycles have been removed using a redesigne d processor core. as a result, every 8051 instruction is executed between 1.5 and 3 ti mes faster than the original for the same crystal speed. typical applications see a speed improvement of 2.5 times using the same code and same crystal. the ds80c320 offers a maximum crystal rate of 33mhz, resul ting in apparent execution speeds of 82.5mhz (approximately 2.5x). the ds80c320/ds80c323 are pin compatible with all th ree packages of the st andard 80c32 and offer the same timer/counters, serial port, and i/o ports. in short, the devices are extremely familiar to 8051 users, but provide the speed of a 16-bit processor. the ds80c320 provides several extras in addition to greater speed. thes e include a second full hardware serial port, seven additional interr upts, programmable watchdog timer, po wer-fail interrupt and reset. the device also provides dual data pointer s (dptrs) to speed block data memory moves. it can also adjust the speed of off-chip data memory access to between two a nd nine machine cycles for flexibility in selecting memory and peripherals. the ds80c320 operating voltage ranges from 4.25v to 5.5v, making it ideal as a high-performance upgrade to existing 5v systems. for applications in which power consumption is critical, the ds80c323 offers the same feature set as the ds80c320, but with 2.7v to 5.5v operation. designers must have two documents to fully use all the features of this device: this data sheet and the high-speed microcontroller user?s guide , available on our website at www.maxim-ic.com/microcontrollers . data sheets contain pin descri ptions, feature overviews, and electrical specifications, whereas our users guides cont ain detailed information a bout device features and operation. ordering information part pb-free/rohs- compl iant temp range max clock speed (mhz) pin-package ds80c320 -mcg ds80c320- mcg+ 0c to +70c 25 40 plastic dip ds80c320-qcg ds80c320-qcg+ 0c to +70c 25 44 plcc ds80c320-ecg ds80c320-ecg+ 0c to +70c 25 44 tqfp ds80c320-mng ds80c320-mng+ -40c to +85c 25 40 plastic dip ds80c320-qng ds80c320-qng+ -40c to +85c 25 44 plcc ds80c320-eng ds80c320-eng+ -40c to +85c 25 44 tqfp ds80c320-mcl ds80c320-mcl+ 0c to +70c 33 40 plastic dip ds80c320-qcl ds80c320-qcl+ 0c to +70c 33 44 plcc ds80c320-ecl ds80c320-ecl+ 0c to +70c 33 44 tqfp ds80c320-mnl ds80c320-mnl+ -40c to +85c 33 40 plastic dip ds80c320-qnl ds80c320-qnl+ -40c to +85c 33 44 plcc DS80C320-ENL DS80C320-ENL+ -40c to +85c 33 44 tqfp ds80c323 -mcd ds80c323- mcd+ 0c to +70c 18 40 plastic dip ds80c323-qcd ds80c323-qcd+ 0c to +70c 18 44 plcc ds80c323-ecd ds80c323-ecd+ 0c to +70c 18 44 tqfp ds80c323-qnd ds80c323-qnd+ -40c to +85c 18 44 plcc ds80c323-end ds80c323-end+ -40c to +85c 18 44 tqfp + denotes a lead(pb)-free/rohs-compliant device. downloaded from: http:///
ds80c320/ds80c323 high-speed/low-power microcontrollers 3 of 38 figure 1. block diagram pin description pin dip plcc tqfp name function 40 44 38 v cc +5v (+3v for ds80c323) 20 22, 23 16, 17 gnd digital circuit ground 9 10 4 rst reset input. the rst input pin contains a schmitt voltage input to recognize external active-high reset inputs. the pin also employs an internal pulldown resistor to allow for a combination of wired or external reset sources. an rc is not required for power-up, as the device provides this function internally. 18 20 14 xtal2 19 21 15 xtal1 crystal oscillator pins. xtal1 and xtal2 provide support for parallel-resonant, at-cut crystals. xtal1 acts also as an input in the event that an external clock source is used in place of a crystal. xtal2 serves as the output of the crystal amplifier. 29 32 26 psen program store-enable output, active low. this signal is commonly connected to external rom memory as a chip enable. psen provides an active-low pulse width of 2.25 xtal1 cycles with a period of four xtal1 cycles. psen is driven high when data memory (ram) is being accessed through the bus and during a reset condition. ds80c320/ ds80c323 downloaded from: http:///
ds80c320/ds80c323 high-speed/low-power microcontrollers 4 of 38 pin description (continued) pin dip plcc tqfp name function 30 33 27 ale address latch-enable output. this pin functions as a clock to latch the external address lsb from the multiplexed address/data bus. this signal is commonly connected to the latch enable of an external 373 family transparent latch. ale has a pulse width of 1.5 xtal1 cycles and a period of four xtal1 cycles. ale is forced high when the device is in a reset condition. 39 43 37 ad0 38 42 36 ad1 37 41 35 ad2 36 40 34 ad3 35 39 33 ad4 34 38 32 ad5 33 37 31 ad6 32 36 30 ad7 port 0, input/output. port 0 is the multiplexed address/data bus. during the time when ale is high, the lsb of a memory address is presented. when ale falls, the port transitions to a bidirectional data bus. this bus is used to read exte rnal rom and read/write external ram memory or peripherals. the port 0 has no true port latch and cannot be written directly by software. the reset condition of port 0 is high. no pullup resistors are needed. port 1, i/o . port 1 functions as both an 8-bit, bidirectional i/o port and an alternate functional interface for timer 2 i/o, new external interrupts, and new serial port 1. the reset condition of port 1 is with all bits at logic 1. in this state, a weak pullup holds the port high. this condition also serves as an input mode , since any external circuit that writes to the port will overcome the weak pullup. when software writes a 0 to any port pin, the device will activate a strong pulldown that remains on until either a 1 is written or a reset occurs. writing a 1 after the port has been at 0 will cause a stro ng transition driver to turn on, followed by a weaker sustaining pu llup. once the momentary strong driver turns off, the port once again becomes the output high (and input) state. the alternate modes of port 1 are outlined as follows: pin dip plcc tqfp port alternate function 1 2 40 p1.0 t2 external i/o for timer/counter 2 2 3 41 p1.1 t2ex timer/counter 2 capture/reload trigger 3 4 42 p1.2 rxd1 serial port 1 input 4 5 43 p1.3 txd1 serial port 1 output 5 6 44 p1.4 int2 external interrupt 2 (positive-edge detect) 6 7 1 p1.5 int3 external interrupt 3 (negative-edge detect) 7 8 2 p1.6 int4 external interrupt 4 (positive-edge detect) 1C8 2C9 40C44, 1C3 p1.0Cp1.7 8 9 3 p1.7 int5 external interrupt 5 (negative-edge detect) downloaded from: http:///
ds80c320/ds80c323 high-speed/low-power microcontrollers 5 of 38 pin description (continued) pin dip plcc tqfp name function 21 24 18 a8 (p2.0) 22 25 19 a9 (p2.1) 23 26 20 a10 (p2.2) 24 27 21 a11 (p2.3) 25 28 22 a12 (p2.4) 26 29 23 a13 (p2.5) 27 30 24 a14 (p2.6) 28 31 25 a15 (p2.7) port 2, output . port 2 serves as the msb for external addressing. p2.7 is a15 and p2.0 is a8. the device will automatically place the msb of an address on p2 for external rom and ram access. although port 2 can be accessed like an ordinary i/o port, the value stored on the port 2 latch will never be seen on the pins (due to memory access). therefore, writing to port 2 in software is only useful for the instructions movx a, @ri or movx @ri, a. these instructions use the port 2 internal latch to supply the external address msb. in this case, the port 2 latch value will be supplied as the address information. port 3, input/output. port 3 functions as both an 8-bit, bidirectional i/o port and an alternate functional interface for external interrupts, serial port 0, timer 0 & 1 inputs, rd and wr strobes. the reset condition of port 3 is with all bits at logic 1. in this state, a weak pullup holds the port high. this condition also serves as an input mode, since any external circuit that writes to the port will overcome the weak pullup. when software wr ites a 0 to any port pin, the device will activate a strong pulldown that remains on until either a 1 is written or a reset occurs. writing a 1 after the port has been at 0 will cause a strong transition driver to turn on, followed by a weaker sustaining pullup. once the momentary strong driver turns off, the port once again becomes both the output high and input state. the alternate modes of port 3 are outlined below: pin dip plcc tqfp port alternate mode 10 11 5 p3.0 rxd0 serial port 0 input 11 13 7 p3.1 txd0 serial port 0 output 12 14 8 p3.2 int0 external interrupt 0 13 15 9 p3.3 int1 external interrupt 1 14 16 10 p3.4 t0 timer 0 external input 15 17 11 p3.5 t1 timer 1 external input 16 18 12 p3.6 wr external data memory write strobe 10C17 11, 13C 19 5, 7C13 p3.0Cp3.7 17 19 13 p3.7 rd external data memory read strobe 31 35 29 ea external access, active-low input. this pin must be connected to ground for proper operation. 12, 34, 1* 6, 28, 39* n.c. no connection (reserved). these pins should not be connected. they are reserved for use with future devices in this family. * these pins are reserved for additi onal ground pins on future products. downloaded from: http:///
ds80c320/ds80c323 high-speed/low-power microcontrollers 6 of 38 80c32 compatibility the ds80c320/ds80c323 are cmos 80c32-compatible microcont rollers designed for high performance. in most cases, the devices will drop into an existing 80c32 design to significantly improve the operation. every effort has been made to keep th e devices familiar to 8032 users, yet they have many new features. in general, software written for ex isting 80c32-based systems will work on the ds80c320 and ds80c323. the exception is critical timing, because the high-speed microcontroller performs its instructions much faster than the original. it may be necessary to use memories w ith faster access times if the same crystal frequency is used. application note 57: ds80c320 memory interface timing is a useful tool to help the embedded system designer select the proper memori es for her or his application. the ds80c320/ds80c323 run the standard 8051 instructio n set and is pin compatible with an 80c32 in any of three standard packages. they also provide the same timer/counter resources, full-duplex serial port, 256 bytes of scratchpad ram, and i/o ports as the standard 80c32. timers will default to a 12 clock-per-cycle operation to keep ti ming compatible with original 8051 systems. however, they can be programmed to run at the new 4 clocks per cycle if desired. new hardware features are accessed using special-f unction registers that do not overlap with standard 80c32 locations. a summary of these sfrs is provided below. the ds80c320/ds80c323 address memory in an identi cal fashion to the standard 80c32. electrical timing appears different due to the high-speed nature of the product. however, th e signals are essentially the same. detailed timing diagrams are provided in the electrical specifications section. this data sheet assumes the user is familiar with the basic features of the standard 80c32. in addition to these standard features, the ds80c320/ds80c323 incl ude many new functions. th is data sheet provides only a summary and overview. detailed descriptions are available in the high-speed microcontroller user?s guide . downloaded from: http:///
ds80c320/ds80c323 high-speed/low-power microcontrollers 7 of 38 figure 2. comparative timing of the ds80c320/ds80c323 and 80c32 ds80c320/ds80c323 timing standard 80c32 timing high-speed operation the ds80c320/ds80c323 are built around a high-speed, 80c32-compatible core. higher speed comes not just from increasing the clock frequency bu t also from a newer, more efficient design. in this updated core, dummy memory cycles have been eliminated. in a conventional 80c32, machine cycles are generated by dividing the clock frequency by 12. in the ds80c320/ds80c323, the same machine cycle is performed in 4 cloc ks. thus the fastest in struction, one machine cy cle, is executed three times faster for the same crystal frequency. note th at these are identical inst ructions. figure 2 shows a comparison of the timing differences. the majority of instructions will see the full 3-to-1 speed improvement. some instructions will get between 1.5x and 2.4x improvement. note that all instructions are faster than the original 80c51. table 1 shows a summary of the instructi on set, including the speed. the numerical average of all op codes is approximately a 2.5-to-1 speed improvement. individual programs are affected differently, depending on the actua l instructions used. speed-sensitive applications would make the most use of instructions that are th ree times faster. however, the sheer number of 3-to-1 improved op codes makes dramatic speed improvements likely for any code. the dual data pointer feature also allows the user to eliminate wast ed instructions when moving blocks of memory. downloaded from: http:///
ds80c320/ds80c323 high-speed/low-power microcontrollers 8 of 38 instruction set summary all instructions in the ds80c320/ ds80c323 perform the same functions as their 80c32 counterparts. their effect on bits, flags, and other status functions is identical. however, the timing of each instruction is different. this applies both in ab solute and relative number of clocks. for absolute timing of real-time events, the timing of software loops will need to be calculated using the table 1. however, counter/timers default to run at the older 12 clocks per increment. therefore, while software runs at higher speed, timer-based events n eed no modification to operate as before. timers can be set to run at 4 clocks per increment cycl e to take advantage of higher speed operation. the relative time of two instructions might be different in the new arch itecture than it was previously. for example, in the original architecture, the movx a, @dptr instruction and the mov direct, direct instruction used two machine cycles or 24 oscillator cycles. therefore, they required the same amount of time. in the ds80c320/ds80c323, the m ovx instruction can be done in two machine cycles or eight oscillator cycles, but the mov direct, direct uses three machine cycles or 12 oscillator cycles. while both are faster than their original counterparts, they now have different execution times from each other. this is because in most cases, the ds80c320/ds80c323 use one cycle for each byte. the user concerned with precise program timing should examine the timing of each instruction for familiarity with the changes. note that a machine cycle now requires just four clocks, and provides one ale pulse per cycle. many instructions require only one cycle, but some require five. in the original architecture, all were one or two cycles except for mul and div. downloaded from: http:///
ds80c320/ds80c323 high-speed/low-power microcontrollers 9 of 38 table 1. instruction set summary symbol function symbol function a accumulator bit direct bit-address rn register r7 to r0 #data 8-bit constant direct internal register address #data 16 16-bit constant addr 16 16-bit destination address @ri internal register pointed to by r0 or r1 (except movx) addr 11 11-bit destination address rel twos complement offset byte instruction byte oscillator cycles instruction byte oscillator cycles arithmatic instructions add a, rn 1 4 inc a 1 4 add a, direct 2 8 inc rn 1 4 add a, @ri 1 4 inc direct 2 8 add a, #data 2 8 inc @ri 1 4 addc a, rn 1 4 inc dptr 1 12 addc a, direct 2 8 dec a 1 4 addc a, @ri 1 4 dec rn 1 4 addc a, #data 2 8 dec direct 2 8 subb a, rn 1 4 dec @ri 1 4 subb a, direct 2 8 mul ab 1 20 subb a, @ri 1 4 div ab 1 20 subb a, #data 2 8 da a 1 4 logical instructions anl a, rn 1 4 xrl a, rn 1 4 anl a, direct 2 8 xrl a, direct 2 8 anl a, @ri 1 4 xrl a, @ri 1 4 anl a, #data 2 8 xrl a, #data 2 8 anl direct, a 2 8 xrl direct, a 2 8 anl direct, #data 3 12 xrl direct, #data 3 12 orl a, rn 1 4 clr a 1 4 orl a, direct 2 8 cpl a 1 4 orl a, @ri 1 4 rl a 1 4 orl a, #data 2 8 rlc a 1 4 orl direct, a 2 8 rr a 1 4 orl direct, #data 3 12 rrc a 1 4 downloaded from: http:///
ds80c320/ds80c323 high-speed/low-power microcontrollers 10 of 38 table 1. instruction set summary (continued) instruction byte oscillator cycles instruction byte oscillator cycles data transfer instructions mov a, rn 1 4 movc a, @a+dptr 1 12 mov a, direct 2 8 movc a, @a+pc 1 12 mov a, @ri 1 4 movx a, @ri 1 8C36* mov a, #data 2 8 movx a, @dptr 1 8C36* mov rn, a 1 4 movx @ri, a 1 8C36* mov rn, direct 2 8 movx @dptr, a 1 8C36* mov rn, #data 2 8 push direct 2 8 mov direct, a 2 8 pop direct 2 8 mov direct, rn 2 8 xch a, rn 1 4 mov direct1, direct2 3 12 xch a, direct 2 8 mov direct, @ri 2 8 xch a, @ri 1 4 mov direct, #data 3 12 xchd a, @ri 1 4 mov @ri, a 1 4 mov @ri, direct 2 8 mov @ri, #data 2 8 mov dptr, #data 16 3 12 bit manipulation instructions clr c 1 4 anl c, bit 2 8 clr bit 2 8 anl c, bit 2 8 setb c 1 4 orl c, bit 2 8 setb bit 2 8 orl c, bit 2 8 cpl c 1 4 mov c, bit 2 8 cpl bit 2 8 mov bit, c 2 8 program branching instructions acall addr 11 2 12 cjne a, direct, rel 3 16 lcall addr 16 3 16 cjne a, #data, rel 3 16 ret 1 16 cjne rn, #data, rel 3 16 reti 1 16 cjne ri, #data, rel 3 16 ajmp addr 11 2 12 nop 1 4 ljmp addr 16 3 16 jc rel 2 12 sjmp rel 2 12 jnc rel 2 12 jmp @a+dptr 1 12 jb bit, rel 3 16 jz rel 2 12 jnb bit, rel 3 16 jnz rel 2 12 jbc bit, rel 3 16 djnz rn, rel 2 12 djnz direct, rel 3 16 * user selectable. downloaded from: http:///
ds80c320/ds80c323 high-speed/low-power microcontrollers 11 of 38 table 1 shows the speed for each class of instruction. note that many of the instructions have multiple op codes. there are 255 op codes for 111 instructions. of the 255 op codes, 159 are three times faster than the original 80c32. while a system that emphasizes thos e instructions will see the most improvement, the large total number that receive a 3 to 1 improvement assure a dramatic speed increase for any system. the speed improvement summary is provided below. speed advantage summary #op codes speed improvement 159 3.0 x 51 1.5 x 43 2.0 x 2 2.4 x 255 average: 2.5 memory access the ds80c320/ds80c323 do not contain on-chip rom a nd 256 bytes of scratchpad ram. off-chip memory is accessed using the multiplexed address/data bus on p0 and the msb address on p2. figure 3 shows a typical memory connection. ti ming diagrams are provided in the electrical specifications section. program memory (rom) is accessed at a fixed rate determined by the crystal frequency and the actual instructions. as previously mentioned, an instruction cycle requi res 4 clocks. data memory (ram) is accessed according to a variable-speed movx instruction as described below. figure 3. typical memory connection downloaded from: http:///
ds80c320/ds80c323 high-speed/low-power microcontrollers 12 of 38 stretch memory cycle the ds80c320/ds80c323 allow the application software to adjust the speed of data memory access. the microcontroller is capable of performing the movx in as little as two instruction cycl es. however, this value can be stretched as needed so that both fast memory and slow memory or peripherals can be accessed with no glue logic. even in high-speed system s, it may not be necessary or desirable to perform data memory access at full speed. in addition, there ar e a variety of memory-mapped peripherals such as lcd displays or uarts that are not fast. the stretch movx is controlled by the clock control register at sfr location 8eh as described below. this allows the user to select a stretch value betw een 0 and 7. a stretch of 0 will result in a two-machine cycle movx. a stretch of 7 will re sult in a movx of nine machine cycles. software can dynamically change this value depending on the particular memory or peripheral. on reset, the stretch value will default to 1, re sulting in a three-cycle m ovx. therefore, ram access will not be performed at full speed. this is a convenience to existing designs that may not have fast ram in place. when maximum speed is desired, the softwa re should select a stretch value of 0. when using very slow ram or peripherals, a larg er stretch value can be selected. note that this affects data memory only and the only way to slow program memory (rom) access is to use a slower crystal. using a stretch value between 1 and 7 causes the microcontroller to stre tch the read/write strobe and all related timing. this results in a wider read/write st robe allowing more time for memory/peripherals to respond. the timing of the variable speed movx is shown in the electrical specifications section. note that full speed access is not the reset default case. table 2 shows the resulting strobe widths for each stretch value. the memory stretch is implemented us ing the clock control spec ial-function register at sfr location 8eh. the stretch value is selected using bits ckcon.2 C0. in the table, these bits are referred to as m2 through m0. the first stretch (def ault) allows the use of common 120ns or 150ns rams without dramatically lengthening the memory access. table 2. data memory cycle stretch values ckcon.2?0 md2 md1 md0 memory cycles rd or wr strobe width in clocks strobe width time at 25mhz (ns) 0 0 0 2 2 80 0 0 1 3 (default) 4 160 0 1 0 4 8 320 0 1 1 5 12 480 1 0 0 6 16 640 1 0 1 7 20 800 1 1 0 8 24 960 1 1 1 9 28 1120 downloaded from: http:///
ds80c320/ds80c323 high-speed/low-power microcontrollers 13 of 38 dual data pointer data memory block moves can be accelerated using the dual data pointer (dptr). the standard 8032 dptr is a 16-bit value that is used to addr ess off-chip data ram or peripherals. in the ds80c320/ds80c323, the standard 16-bit data pointer is called dptr0 a nd is located at sfr addresses 82h and 83h. these are the standard locations. the new dptr is located at sfr 84h and 85h and is called dptr1. the dptr select bit (dps) chooses the active pointer and is located at the lsb of the sfr location 86h. no other bits in register 86h have any effect a nd are set to 0. the user switches between data pointers by toggling th e lsb of register 86h. the increment (inc) instruction is the fastest way to accomplish this. all dptr-rel ated instructions use the currentl y selected dptr for any activity. therefore only one instruction is required to switch from a source to a destination address. using the dual-data pointer saves code from needing to save source and destin ation addresses when doing a block move. once loaded, the software simply switches betw een dptr and 1. the releva nt register locations are as follows. dpl 82h low byte original dptr dph 83h high byte original dptr dpl1 84h low byte new dptr dph1 85h high byte new dptr dps 86h dptr select (lsb) sample code listed below illustrates the saving from using the dual dptr. the example program was original code written for an 8051 and requires a total of 1869 ds80c320/ds80c323 machine cycles. this takes 299 ? s to execute at 25mhz. the new code using the dual dptr requires only 1097 machine cycles taking 175.5 ? s. the dual dptr saves 772 machine cycles or 123.5 ? s for a 64-byte block move. since each pass through the loop saves 12 machine cycl es when compared to the single dptr approach, larger blocks gain more efficiency using this feature. 64-byte block move with out dual data pointer ; sh and sl are high and low byte source address. ; dh and dl are high and low byte of destination address. # cycles mov r5, #64d ; number of bytes to move 2 mov dptr, #shsl ; load source address 3 mov r1, #sl ; save low byte of source 2 mov r2, #sh ; save high byte of source 2 mov r3, #dl ; save low byte of destination 2 mov r4, #dh ; save high byte of destination 2 move: ; this loop is performed the number of times loaded into r5, in this example 64 movx a, @dptr ; read source data byte 2 mov r1, dpl ; save new source pointer 2 mov r2, dph ; 2 mov dpl, r3 ; load new destination 2 mov dph, r4 ; 2 movx @dptr, a ; write data to destination 2 inc dptr ; next destination address 3 mov r3, dpl ; save new destination pointer 2 mov r4, dph ; 2 mov dpl, r1 ; get new source pointer 2 mov dph, r2 ; 2 inc dptr ; next source address 3 djnz r5, move ; finished with table? 3 downloaded from: http:///
ds80c320/ds80c323 high-speed/low-power microcontrollers 14 of 38 64-byte block move with dual data pointer ; sh and sl are high and low byte source address. ; dh and dl are high and low byte of destination address. ; dps is the data pointer select. reset condition is dps=0, dptr0 is selected. # cycles equ dps, #86h ; tell assembler about dps mov r5, #64 ; number of bytes to move 2 mov dptr, #dhdl ; load destination address 3 inc dps ; change active dptr 2 mov dptr, #shsl ; load source address 2 move: ; this loop is performed the number of times loaded into r5, in this example 64 movx a, @dptr ; read source data byte 2 inc dps ; change dptr to destination 2 movx @dptr, a ; write data to destination 2 inc dptr ; next destination address 3 inc dps ; change data pointer to source 2 inc dptr ; next source address 3 djnz r5, move ; finished with table? 3 peripheral overview peripherals in the ds80c320/ds80c323 are accessed usin g the sfrs. the devices provide several of the most commonly needed peripheral functions in micr ocomputer-based systems. these functions are new to the 80c32 family and include a second serial por t, power-fail reset, pow er-fail interrupt, and a programmable watchdog timer. these are briefly descri bed in the following paragraphs. more details are available in the high-speed microcontroller user?s guide . serial ports the ds80c320/ds80c323 provide a se rial port (uart) that is identical to the 80c32. many applications require serial communication with multiple devices. therefore, a second hardware serial port is provided that is a full duplic ate of the standard one. it optiona lly uses pins p1.2 (rxd1) and p1.3 (txd1). this port has duplicate control functions in cluded in new sfr locations. the second serial port operates in a comparable manner with the first. both can operate simultaneously but can be at different baud rates. the second serial port has similar control registers (scon1 at c0h, sbuf1 at c1h) to the original. one difference is that for timer-based baud rates, the or iginal serial port can us e timer 1 or timer 2 to generate baud rates. this is selected via sfr bits. the new serial port can only use timer 1. timer-rate control one important difference exists between the ds80c320/ds80c323 and 80c32 re garding timers. the original 80c32 used a 12 clock-per-cycle scheme for timers and consequently for some serial baud rates (depending on the mode). the ds80c320/ds80c323 archit ecture normally runs using 4 clocks per cycle. however, in the area of timers, it will default to a 12 clock-per-cycle scheme on a reset. this allows existing code with real-time dependencies such as baud rates to operate properly. if an application needs higher speed timers or serial baud rates, the tim ers can be set to run at the 4-clock rate. the clock control register (ckcon - 8eh) determines these timer speeds. when the relevant ckcon bit is a logic 1, the device uses 4 clocks per cycle to generate timer speeds. when the control bit is set to a 0, the device uses 12 clocks for timer speeds. the reset condition is a 0. ckcon.5 selects the speed of timer 2. ckcon.4 selects timer 1 and ckcon.3 select s timer 0. note that unless a user desires very fast timing, it is unnecessary to alter these bits. note that the timer controls are independent. downloaded from: http:///
ds80c320/ds80c323 high-speed/low-power microcontrollers 15 of 38 power-fail reset the ds80c320/ds80c323 incorporate a precision bandgap voltage reference to determine when v cc is out of tolerance. while powering up, internal circu its will hold the device in a reset state until v cc rises above the v rst reset threshold. once v cc is above this level, the oscilla tor will begin running. an internal reset circuit will then count 65,536 clocks to allow time for power an d the oscillator to stabilize. the microcontroller will then exit the reset condition. no ex ternal components are needed to generate a power on reset. during power-down or duri ng a severe power glitch, as v cc falls below v rst , the microcontroller will also generate its own reset. it wi ll hold the reset condition as long as power remains below the threshold. this reset will occur automati cally, needing no action from the user or from the software. see the electrical specifications section for the exact value of v rst . power-fail interrupt the same reference that generates a precision reset th reshold can also generate an optional early warning power-fail interrupt (pfi). when enabled by the application software, this interrupt always has the highest priority. on detecting that the v cc has dropped below v pfw and that the pfi is enabled, the processor will vector to rom address 0033h. the pfi enable is located in the watchdog control sfr (wdcon to d8h). setting wdcon.5 to logic 1 will enab le the pfi. the application software can also read a flag at wdcon.4. this bit is set when a pfi condition has occurred. the flag is independent of the interrupt enable and software must manually clear it. watchdog timer for applications that cannot afford to run out of control, the ds80c320/ds80c323 incorporate a programmable watchdog timer circuit. the watchdog timer circuit resets the microcontroller if software fails to reset the watchdog before the selected time interval has elapsed. the user selects one of four timeout values. after enabling the watchdog, software mu st reset the timer prior to expiration of the interval, or the cpu will be reset. both the wa tchdog enable and the watchdog reset bits are protected by a timed access circuit. this prevents accidentally cleari ng the watchdog. timeout values are precise since they are related to th e crystal frequency as shown in tabl e 3. for reference, the time periods at 25mhz are also shown. the watchdog timer also provides a us eful option for systems that may not require a reset. if enabled, then 512 clocks before giving a reset, the watchdog will give an interrupt. the interrupt can also serve as a convenient time-base generator, or be used to wake-up the proc essor from idle mode. the watchdog function is controlled in the clock control (ckc on to 8eh), watchdog contro l (wdcon to d8h), and extended interrupt enable (eie to e8h) sfrs. ckcon.7 and ckcon.6 are called wd1 and wd0, respectively, and are used to select the watchdog timeout pe riod as shown in table 3. table 3. watchdog timeout values wd1 wd0 interrupt timeout time (at 25mhz) reset timeout time (at 25mhz) 0 0 2 17 clocks 5.243ms 2 17 + 512 clocks 5.263ms j 0 1 2 20 clocks 41.94ms 2 20 + 512 clocks 41.96ms 1 0 2 23 clocks 335.54ms 2 23 + 512 clocks 335.56ms 1 1 2 26 clocks 2684.35ms 2 26 + 512 clocks 2684.38ms as table 3 shows, the watchdog timer uses the crystal frequency as a time base. a user selects one of four counter values to determine the tim eout. these clock counter lengths are 2 17 = 131,072 clocks; 2 20 = 1,048,576; 2 23 = 8,388,608 clocks; or 2 26 = 67,108,864 clocks. the times shown in table 4 are with downloaded from: http:///
ds80c320/ds80c323 high-speed/low-power microcontrollers 16 of 38 a 25mhz crystal frequency. note that once the c ounter chain has reached a conclusion, the optional interrupt is generated. regard less of whether the user en ables this interrupt, ther e are then 512 clocks left until a reset occurs. there are 5 c ontrol bits in special function regi sters that affect the watchdog timer and two status flags that repor t to the user. the reset watchdog timer bit (wdcon.0) should be asserted prior to modifying the watchdog timer mode select bits (wd1, wd0) to avoid corruption of the watchdog count. wdif (wdcon.3) is the interrupt flag that is se t when there are 512 clocks remaining until a reset occurs. wtrf (wdcon.2) is the flag that is set when a watchdog reset has occurred. this allows the application software to determine the source of a reset. setting the ewt (wdcon.1) bit enables the watchdog timer. the bit is protected by timed access. setting the rwt (wdcon.0) bit restarts the watc hdog timer for another full interval. application software must set this bit prior to the timeout. as mentioned previously, wd1 and 0 (ckcon .7 and 6) select the timeout. finally, the watchdog in terrupt is enabled using ewdi (eie.4). interrupts the ds80c320/ds80c323 provide 13 sources of interrupt with three priority levels. the power-fail interrupt (pfi), if enabled, always has the highest priority. there are two remaining user-selectable priorities: high and low. if two in terrupts that have the same priori ty occur simultaneously, the natural precedence given in table 4 determines which is ac ted upon. except for the pfi, all interrupts that are new to the 8051 family have a lower na tural priority than the originals. table 4. interrupt priority name function vector natural priority old/new pfi power-fail interrupt 33h j 1 new int0 external interrupt 0 03h 2 old tf0 timer 0 0bh 3 old int1 external interrupt 1 13h 4 old tf1 timer 1 1bh 5 old scon0 ti0 or ri0 from serial port 0 23h 6 old tf2 timer 2 2bh 7 old scon1 ti1 or ri1 from serial port 1 3bh 8 new int2 external interrupt 2 43h 9 new int3 external interrupt 3 4bh 10 new int4 external interrupt 4 53h 11 new int5 external interrupt 5 5bh 12 new wdti watchdog timeout interrupt 63h 13 new downloaded from: http:///
ds80c320/ds80c323 high-speed/low-power microcontrollers 17 of 38 power management the ds80c320/ds80c323 provide the sta ndard idle and power-down (stop) modes that are available on the standard 80c32. however, the device has enhancem ents that make these modes more useful, and allow more power saving. the idle mode is invoked by setting the lsb of the power control regist er (pcon to 87h). idle will leave internal clocks, serial port and timer running. no memory access will be performed so power is dramatically reduced. since clocks are running, the idle power cons umption is related to crystal frequency. it should be approximate ly one-half the operational power. the cpu can exit the idle state with any interrupt or a reset. the power-down or stop mode is invoked by setting the pcon.1 bit. stop mode is a lower power state than idle since it turns o ff all internal clocking. the i cc of a standard stop mode is approximately 1 a but is specified in the electrical specifications section. the cpu will exit stop mode from an external interrupt or a reset condition. note that internally genera ted interrupts (timer, serial port, watchdog) are not useful in idle or stop since they require clocking activity. idle mode enhancements a simple enhancement to idle mode makes it substa ntially more useful. the innovation involves not the idle mode itself, but the watchdog timer. as men tioned above, the watchdog timer provides an optional interrupt capability. this in terrupt can provide a periodic interval timer to bring the ds80c320/ds80c323 out of idle mode. th is can be useful ev en if the watchdog is not normally used. by enabling the watchdog timer and its interrupt prior to invoking idle, a user ca n periodically come out of idle perform an operation, then return to idle until the next operation. this wi ll lower the overall power consumption. when using the watchdog interrupt to can cel the idle state, make sure to restart the watchdog timer or it will cause a reset. stop mode enhancements the ds80c320/ds80c323 provide two enhancements to the stop mode. as documented above, the device provides a bandgap reference to determine po wer-fail interrupt and reset thresholds. the default state is that the bandgap referenc e is off when stop mode is invoked. this allows the extremely low power state mentioned above. a user can optionally choose to have the ba ndgap enabled during stop mode. this means that pfi and power-fail reset will be activated and are valid means for leaving stop mode. in stop mode with the bandgap on, i cc will be approximately 50 ? a compared with 1 ? a with the bandgap off. if a user does not require a power-fail reset or interrupt while in stop mode, the bandgap can remain turned off. note that only the most power sensitive applications should turn off the bandgap, as this results in an uncontrolle d power-down condition. the control of the bandgap reference is located in th e extended interrupt flag register (exif to 91h). setting bgs (exif.0) to a 1 will leave the bandgap reference enabled during stop mode. the default or reset condition is with the bit at a logic 0. this results in the bandga p being turned off during stop mode. note that this bit has no control of the reference during full power or idle modes. be aware that the ds80c320 and ds80c323 require that the reset watchdog timer bit (rwt;wdcon.0) be set downloaded from: http:///
ds80c320/ds80c323 high-speed/low-power microcontrollers 18 of 38 immediately preceding the setting of the stop bit to guarantee a correct power-on delay when exiting stop mode. the second feature allows an additi onal power saving option. this is the ability to start instantly when exiting stop mode. it is accomplished using an internal ring oscillator that can be used when exiting stop mode in response to an interrupt. the bene fit of the ring oscillator is as follows. using stop mode turns off the crystal oscillator and all intern al clocks to save pow er. this requires that the oscillator be restarted when exiting stop mode. actual start-up ti me is crystal dependent, but is normally at least 4ms. a common recommendation is 10m s. in an application th at will wakeup, perform a short operation, then return to sleep, the crystal start up can be longer th an the real transaction. however, the ring oscillator will start instantly. the user can pe rform a simple operation and return to sleep before the crystal has even stabili zed. if the ring is used to start and th e processor remains running, hardware will automatically switch to the crystal once a power-on re set interval (65,536 clocks ) has expired. this value is used to guarantee stability even though power is not being cycled. if the user returns to stop mode prior to switching of crystal, then al l clocks will be turned off again. the ring oscillator runs at approximate ly 3mhz (1.5mhz at 3v) but will not be a precision value. no real- time precision operations (including serial communica tion) should be conducted during this ring period. figure 4 shows how the operation would compare when using the ring, and when starting up normally. the default state is to co me out of stop mode without using the ring oscillator. this function is controlled using the rgsl - ring se lect bit at exif.1 (exif to 91h). when exif.1 is set, the ring oscillator will be used to come out of stop mode quickl y. as mentioned above, the processor will automatically switch from the ring (if enabled) to the crystal after a delay of 65,536 crystal clocks. for a 3.57mhz crystal, this is approximately 18ms. the processor sets a flag called rgmd - ring mode to tell software that the ring is being used. this bit at exif.2 will be logic 1 when the ring is in use. no serial communication or precision timing should be atte mpted while this bit is set, since the operating frequency is not precise. downloaded from: http:///
ds80c320/ds80c323 high-speed/low-power microcontrollers 19 of 38 figure 4. ring oscillator startup timed access protection selected sfr bits are critical to operation, making it desirable to protect against an accidental write operation. the timed access procedure prevents an er rant cpu from accidentally altering a bit that would cause difficulty. the timed acce ss procedure requires that the write of a protected bit be preceded by the following instructions: mov 0c7h, #0aah mov 0c7h, #55h by writing an aah followed by a 55h to the timed acces s register (location c7h), the hardware opens a three-cycle window that allows software to modify one of the protected b its. if the instru ction that seeks to modify the protected bit is not immediately proceed ed by these instructions, the write will not take effect. the protected bits are: exif.0 bgs bandgap select wdcon.6 por power-on reset flag wdcon.1 ewt enable watchdog wdcon.0 rwt reset watchdog wdcon.3 wdif watchdog interrupt flag diagram assumes that the operation following stop requires less than 18ms complete. downloaded from: http:///
ds80c320/ds80c323 high-speed/low-power microcontrollers 20 of 38 special-function registers most special features of the ds 80c320/ds80c323 or 80c32 are controlle d by bits in the sfrs, allowing the devices to add many features but use the same in struction set. when writing software to use a new feature, the sfr must be defined to an assembler or compiler using an equate statement. this is the only change needed to access the new function. the ds80c320/ds80c323 duplicate the sfrs that are contained in the standard 80c32. table 5 shows the register addresses a nd bit locations. many are standard 80c32 registers. the high-speed microcontroller user?s guide describes all sfrs. table 5. special-functi on register locations register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 address sp 81h dpl 82h dph 83h dpl1 84h dph1 85h dps 0 0 0 0 0 0 0 sel 86h pcon smod_0 smod0 ? ? gf1 gf0 stop idle 87h tcon tf1 tr1 tf0 tr0 ie1 it1 ie0 it0 88h tmod gate c/ t m1 m0 gate c/ t m1 m0 89h tl0 8ah tl1 8bh th0 8ch th1 8dh ckcon wd1 wd0 t2m t1m t0m md2 md1 md0 8eh p1 p1.7 p1.6 p1.5 p1.4 p1.3 p1.2 p1.1 p1.0 90h exif ie5 ie4 ie3 ie2 ? rgmd rgsl bgs 91h scon0 sm0/fe_0 sm1_0 sm2_0 ren_0 tb8_0 rb8_0 ti_0 ri_0 98h sbuf0 99h p2 p2.0 p2.6 p2.5 p2.4 p2.3 p2.2 p2.1 p2.0 a0h ie ea es1 et2 es0 et1 ex1 et0 ex0 a8h saddr0 a9h saddr1 aah p3 p3.7 p3.6 p3.5 p3.4 p3.3 p3.2 p3.1 p3.0 b0h ip ? ps1 pt2 ps0 pt1 px1 pt0 px0 b8h saden0 b9h saden1 bah scon1 sm0/fe_0 sm1_0 sm2_0 ren_0 tb8_0 rb8_0 ti_0 ri_0 c0h sbuf1 c1h status pip hip lip 1 1 1 1 1 c5h ta c7h t2con tf2 exf2 rclk tclk exen2 tr2 c/ t2 cp/ rl2 c8h t2mod ? ? ? ? ? ? t2oe dcen c9h rcap2l cah rcap2h cbh tl2 cch th2 cdh psw cy ac f0 rs1 rs0 ov fl p d0h wdcon smod_1 por epfi pfi wdif wtrf ewt rwt d8h acc e0h eie ? ? ? ewdi ex5 ex4 ex3 ex2 e8h b f0h eip ? ? ? pwdi px5 px4 px3 px2 f8h downloaded from: http:///
ds80c320/ds80c323 high-speed/low-power microcontrollers 21 of 38 electrical specifications absolute maximum ratings voltage range on any pin relative to ground-0.3v to (v cc + 0.5v) voltage range on v cc relative to ground..-0.3v to +6.0v operating temperature range .-40c to +85c storage temperature range ..-55c to +125c soldering temperature. see ipc/jedec j-std-020 specification this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in t he operation sections of this specif ication is not implied. exposure to absolute ma ximum rating conditions for extended periods of time may affect reliability. dc electrical characteristicsds80c320 (v cc = 4.5v to 5.5v, t a = -40c to +85c.) parameter symbol min typ max units notes operating supply voltage v cc 4.5 5.0 5.5 v 1 power-fail warning voltage v pfw 4.25 4.38 4.55 v 1 minimum operating voltage v rst 4.0 4.1 4.25 v 1, 12 supply current active mode at 25mhz i cc 30 45 ma 2 supply current idle mode at 25mhz i idle 15 25 ma 3 supply current active mode at 33mhz i cc 35 ma 2 supply current idle mode at 33mhz i idle 20 ma 3 supply current stop mode, bandgap reference disabled i stop 0.01 1 a 4 supply current stop mode, bandgap reference enabled i spbg 50 80 a 4, 10 input low level v il -0.3 +0.8 v 1 input high level (except xtal1 and rst) v ih1 2.0 v cc + 0.3 v 1 input high level xtal1 and rst v ih2 3.5 v cc + 0.3 v 1 output-low voltage ports 1, 3 at i ol = 1.6ma v ol1 0.45 v 1 output-low voltage ports 0, 2, ale, psen at i ol = 3.2ma v ol2 0.45 v 1, 5 output-high voltage ports 1, 3, ale, psen at i oh = -50a v oh1 2.4 v 1, 6 output high voltage ports 1, 3 at i oh = -1.5ma v oh2 2.4 v 1, 7 output-high voltage ports 0, 2, ale, psen at i oh = -8ma v oh3 2.4 v 1, 5 input low current ports 1, 3 at 0.45v i il -55 a 11 transition current from 1 to 0 ports 1, 3 at 2v i tl -650 a 8 input leakage port 0, bus mode i l -300 +300 a 9 rst pulldown resistance r rst 50 170 k ? downloaded from: http:///
ds80c320/ds80c323 high-speed/low-power microcontrollers 22 of 38 notes for ds80c320 dc elec trical characteristics all parameters apply to both commercial and in dustrial temperature operation unless ot herwise noted. specifications to -40c are guaranteed by design an d are not production tested. 1. all voltages are referenced to ground. 2. active current is measured with a 25m hz clock source driving xtal1, v cc = rst = 5.5v, all other pins disconnected. 3. idle mode current is measured with a 25mhz clock source driving xtal1, v cc = 5.5v, rst at ground, all other pins disconnected. 4. stop mode current measured w ith xtal1 and rst grounded, v cc = 5.5v, all other pins disconnected. 5. when addressing external memory. this specification only applies to the first clock cycle following transition. 6. rst = v cc . this condition mimics operation of pins in i/o mode. 7. during a 0-to-1 transition, a one-shot drives the ports ha rd for two clock cycles. this measurement reflects port in transition mode. 8. ports 1 and 3 source transition current when being pulled down externally. it reaches its maximum at approximately 2v. 9. 0.45 ds80c320/ds80c323 high-speed/low-power microcontrollers 23 of 38 ac characteristicsds80c320 33mhz variable clock parameter symbol min max min max units external oscillator 0 33 0 33 oscillator frequency external crystal 1/t clcl 1 33 1 33 mhz ale pulse width t lhll 34 1.5t clcl -11 ns port 0 address valid to ale low t avll 4 0.5t clcl -11 ns address hold after ale low t llax1 2 (note 5) 0.25t clcl -5 (note 5) ns address hold after ale low for movx wr t llax2 6 0.5t clcl -9 ns ale low to valid instruction in t lliv 49 2.5t clcl -27 ns ale low to psen low t llpl 0.5 0.25t clcl -7 ns psen pulse width t plph 61 2.25t clcl -7 ns psen low to valid instruction in t pliv 48 2.25t clcl -21 ns input instruction hold after psen t pxix 0 0 ns input instruction float after psen t pxiz 25 t clcl -5 ns port 0 address to valid instruction in t aviv1 64 3t clcl -27 ns port 2 address to valid instruction in t aviv2 73 3.5t clcl -33 ns psen low to address float t plaz (note 5) (note 5) ns notes for ds80c320 ac elec trical characteristics all parameters apply to both commercial and in dustrial temperature operation unless ot herwise noted. specifications to -40c are guaranteed by design and are not production tested. ac electrical characteristics assume 50% duty cycle for the oscillator, oscillator frequency > 16mhz, and are not 100% tested, but are guaranteed by design. 1. all signals rated over operating temperature at 33mhz. 2. all signals characterized with load cap acitance of 80pf except port 0, ale, psen , rd and wr at 100pf. note that loading should be approximately equal for valid timing. 3. interfacing to memory devices with float times (turn off times) over 30ns may cause contention. this will not damage the parts but will cause an increase in operating current. 4. specifications assume a 50% duty cycle for the oscilla tor. port 2 timing will change with the duty cycle variations. 5. address is held in a weak latch until over driven by external memory. downloaded from: http:///
ds80c320/ds80c323 high-speed/low-power microcontrollers 24 of 38 movx characteristicsds80c320 variable clock parameter symbol min max units stretch 2t clcl -11 t mcs =0 rd pulse width t rlrh t mcs -11 ns t mcs >0 2t clcl -11 t mcs =0 wr pulse width t wlwh t mcs -11 ns t mcs >0 2t clcl -25 t mcs =0 rd low to valid data in t rldv t mcs -25 ns t mcs >0 data hold after read t rhdx 0 ns t clcl -5 t mcs =0 data float after read t rhdz 2t clcl -5 ns t mcs >0 2.5t clcl -27 t mcs =0 ale low to valid data in t lldv 1.5t clcl -28+t mcs ns t mcs >0 3t clcl -27 t mcs =0 port 0 address to valid data in t avdv1 2t clcl -31+t mcs ns t mcs >0 3.5t clcl -32 t mcs =0 port 2 address to valid data in t avdv2 2.5t clcl -34+t mcs ns t mcs >0 0.5t clcl -8 0.5t clcl +6 t mcs =0 ale low to rd or wr low t llwl 1.5t clcl -7 1.5t clcl +8 ns t mcs >0 t clcl -11 t mcs =0 port 0 address valid to rd or wr low t avwl1 2t clcl -10 ns t mcs >0 1.5t clcl -9 t mcs =0 port 2 address valid to rd or wr low t avwl2 2.5t clcl -13 ns t mcs >0 -9 t mcs =0 data valid to wr transition t qvwx t clcl -10 ns t mcs >0 t clcl -12 t mcs =0 data hold after write t whqx 2t clcl -7 ns t mcs >0 rd low to address float t rlaz (note 5) ns 0 10 t mcs =0 rd or wr high to ale high t whlh t clcl -5 t clcl +11 ns t mcs >0 note: t mcs is a time period related to the stretch memory cy cle selection. the following table shows the value of t mcs for each stretch selection. m2 m1 m0 movx cycles t mcs 0 0 0 2 machine cycles 0 0 0 1 3 machine cycles (default) 4 t clcl 0 1 0 4 machine cycles 8 t clcl 0 1 1 5 machine cycles 12 t clcl 1 0 0 6 machine cycles 16 t clcl 1 0 1 7 machine cycles 20 t clcl 1 1 0 8 machine cycles 24 t clcl 1 1 1 9 machine cycles 28 t clcl downloaded from: http:///
ds80c320/ds80c323 high-speed/low-power microcontrollers 25 of 38 dc electrical characteristicsds80c323 parameter symbol min typ max units notes operating supply voltage v cc 2.7 3.0 5.5 v 1 power-fail warning voltage v pfw 2.6 2.7 2.8 v 1 minimum operating voltage v rst 2.5 2.6 2.7 v 1, 12 supply current active mode at 18mhz i cc 10 ma 2 supply current idle mode at 18mhz i idle 6 ma 3 supply current stop mode, bandgap reference disabled i stop 0.1 a 2 supply current stop mode, bandgap reference enabled i spbg 40 a 4, 10 input low level v il -0.3 +0.2 x v cc v 1 input high level (except xtal1 and rst) v ih1 0.7 x v cc v cc +0.3 v 1 input high level xtal1 and rst v ih2 0.7 x v cc +0.25v v cc +0.3 v 1 output low voltage ports 1, 3 at i ol = 1.6ma v ol1 0.4 v 1 output low voltage ports 0, 2, psen /ale at i ol = 3.2ma v ol2 0.4 v 1, 5 output high voltage ports 1, 3, psen /ale at i oh = -15a v oh1 v dd -0.4v v 1, 6 output high voltage ports 1, 3 at i oh = -1.5ma v oh2 v dd -0.4v v 1, 7 output high voltage ports 0, 2, psen /ale at i oh = -2ma v oh3 v dd -0.4v v 1, 5 input low current ports 1, 3 at 0.45v i il -30 a 11 transition current from 1 ? 0, ports 1, 3 at 2v i tl -400 a 8 input leakage port 0, bus mode i l -300 +300 a 9 rst pulldown resistance r rst 50 170 k ? notes for ds80c323 dc elec trical characteristics all parameters apply to both commercial and in dustrial temperature operation unless ot herwise noted. specifications to -40c are guaranteed by design and are not production tested. device oper ating range is 2.7v to 5.5v. dc electrical specifications ar e for operation 2.7v to 3.3v. 1. all voltages are referenced to ground. 2. active mode current is measured with an 18mhz clock source driving xtal1, v cc = rst = 3.3v, all other pins disconnected. 3. idle mode current is measured with an 18mhz clock source driving xtal1, v cc = 3.3v, all other pins disconnected. 4. stop mode current measured w ith xtal1 and rst grounded, v cc = 3.3v, all other pins disconnected. 5. when addressing external memory. this specification only applies to the first clock cycle following the transition. downloaded from: http:///
ds80c320/ds80c323 high-speed/low-power microcontrollers 26 of 38 notes for ds80c323 dc electrical characteristics (continued) all parameters apply to both commercial and in dustrial temperature operation unless ot herwise noted. specifications to -40c are guaranteed by design and are not production tested. device oper ating range is 2.7v to 5.5v. dc electrical specifications ar e for operation 2.7v to 3.3v. 6. rst = v cc . this condition mimics operation of pins in i/o mode. 7. during a 0-to-1 transition, a one-shot drives the ports ha rd for two clock cycles. this measurement reflects port in transition mode. 8. ports 1, 2, and 3 source transition current when bei ng pulled down externally. it reaches its maximum at approximately 2v. 9. v in between ground and v cc - 0.3v. not a high-impedance input. this port is a weak address latch because port 0 is dedicated as an address bus on the ds80c323. p eak current occurs near the input transition point of the latch, approximately 2v. 10. over the industrial temperature range, this specification has a maximum value of 200 ? a. 11. this is the current from an external circuit to hold a logic low level on an i/o pin while the corresponding port latch bit is set to 1. this is only the current required to hold the low level; transitions from 1 to 0 on an i/o pin will also have to overcome the transition current. 12. device operating range is 2.7v to 5.5v, however device is tested to 2.5v to ensure proper operation at minimum v rst . downloaded from: http:///
ds80c320/ds80c323 high-speed/low-power microcontrollers 27 of 38 ac electrical characteristicsds80c323 18 mhz variable clock parameter symbol min max min max units external oscillator 0 18 0 18 oscillator frequency external crystal 1/t clcl 1 18 1 18 mhz ale pulse width t lhll 68 1.5t clcl -15 ns port 0 address valid to ale low t avll 16 0.5t clcl -11 ns address hold after ale low t llax1 6 (note 5) 0.25t clcl -8 (note 5) ns address hold after ale low for movx wr t llax2 14 0.5t clcl -13 ns ale low to valid instruction in t lliv 93 2.5t clcl -46 ns ale low to psen low t llpl 4 0.25t clcl -10 ns psen pulse width t plph 118 2.25t clcl -7 ns psen low to valid instruction in t pliv 87 2.25t clcl -38 ns input instruction hold after psen t pxix 0 0 ns input instruction float after psen t pxiz 51 t clcl -5 ns port 0 address to valid instruction in t aviv1 128 3t clcl -39 ns port 2 address to valid instruction in t aviv2 139 3.5t clcl -56 ns psen low to address float t plaz (note 5) (note 5) ns notes for ds80c323 ac elec trical characteristics all parameters apply to both commercial and in dustrial temperature operation unless ot herwise noted. specifications to -40c are guaranteed by design and are not production tested. ac electrical characteristics assume 50% duty cycle for the oscillator, oscillator frequency > 16mhz, and are not 100% pr oduction tested, but ar e guaranteed by design. 1. all signals rated over operating temperature at 18mhz. 2. all signals characterized with load cap acitance of 80pf except port 0, ale, psen , rd , and wr at 100pf. note that loading should be approximately equal for valid timing. 3. interfacing to memory devices with float times (turn off times) over 35ns may cause contention. this will not damage the parts, but will cause an increase in operating current. 4. specifications assume a 50% duty cycle for the oscilla tor. port 2 timing will change with the duty cycle variations. 5. address is held in a weak latch un til over-driven by external memory. downloaded from: http:///
ds80c320/ds80c323 high-speed/low-power microcontrollers 28 of 38 movx characteristicsds80c323 variable clock parameter symbol min max units stretch 2t clcl -11 t mcs =0 rd pulse width t rlrh t mcs -11 ns t mcs >0 2t clcl -11 t mcs =0 wr pulse width t wlwh t mcs -11 ns t mcs >0 2t clcl -32 t mcs =0 rd low to valid data in t rldv t mcs -36 ns t mcs >0 data hold after read t rhdx 0 ns t clcl -5 t mcs =0 data float after read t rhdz 2t clcl -7 ns t mcs >0 2.5t clcl -43 t mcs =0 ale low to valid data in t lldv 1.5t clcl -45+t mcs ns t mcs >0 3t clcl -40 t mcs =0 port 0 address to valid data in t avdv1 2t clcl -42+t mcs ns t mcs >0 3.5t clcl -58 t mcs =0 port 2 address to valid data in t avdv2 2.5t clcl -59+t mcs ns t mcs >0 0.5t clcl -18 0.5t clcl +7 t mcs =0 ale low to rd or wr low t llwl 1.5t clcl -11 1.5t clcl +8 ns t mcs >0 t clcl -10 t mcs =0 port 0 address valid to rd or wr low t avwl1 2t clcl -10 ns t mcs >0 1.5t clcl -27 t mcs =0 port 2 address valid to rd or wr low t avwl2 2.5t clcl -25 ns t mcs >0 -14 t mcs =0 data valid to wr transition t qvwx t clcl -13 ns t mcs >0 t clcl -15 t mcs =0 data hold after write t whqx 2t clcl -13 ns t mcs >0 rd low to address float t rlaz (note 5) ns -1 14 t mcs =0 rd or wr high to ale high t whlh t clcl -5 t clcl +16 ns t mcs >0 note: t mcs is a time period related to the stretch memory cy cle selection. the following table shows the value of t mcs for each stretch selection. m2 m1 m0 movx cycles t mcs 0 0 0 2 machine cycles 0 0 0 1 3 machine cycles (default) 4 t clcl 0 1 0 4 machine cycles 8 t clcl 0 1 1 5 machine cycles 12 t clcl 1 0 0 6 machine cycles 16 t clcl 1 0 1 7 machine cycles 20 t clcl 1 1 0 8 machine cycles 24 t clcl 1 1 1 9 machine cycles 28 t clcl downloaded from: http:///
ds80c320/ds80c323 high-speed/low-power microcontrollers 29 of 38 external clock characteristics parameter symbol min typ max units clock high time t chcx 10 ns clock low time t clcx 10 ns clock rise time t clch 5 ns clock fall time t chcl 5 ns serial port mode 0 timing characteristics parameter symbol conditions min typ max units sm2 = 0; 12 clocks per cycle 12t clcl serial port clock cycle time t xlxl sm2 = 1; 4 clocks per cycle 4t clcl ns sm2 = 0 12 clocks per cycle 10t clcl output data setup to clock rising edge t qvxh sm2 = 1; 4 clocks per cycle 3t clcl ns sm2 = 0 12 clocks per cycle 2t clcl output data hold from clock rising t xhqx sm2 = 1; 4 clocks per cycle t clcl ns sm2 = 0; 12 clocks per cycle t clcl input data hold after clock rising t xhdx sm2 = 1; 4 clocks per cycle t clcl ns sm2 = 0; 12 clocks per cycle 11t clcl clock rising edge to input data valid t xhdv sm2 = 1 4 clocks per cycle 2t clcl ns explanation of ac symbols in an effort to remain compatible with the original 8051 family, this devi ce specifies the same parameter as such devices, using the same symbols. for completeness, the following is an explanation of the symbols. t time a address c clock d input data h logic level high l logic level low i instruction p psen q output data r rd signal v valid w wr signal x no longer a valid logic level z tri-state downloaded from: http:///
ds80c320/ds80c323 high-speed/low-power microcontrollers 30 of 38 power-cycle timing characteristics parameter symbol min typ max units notes crystal startup time t csu 1.8 ms 1 power-on reset delay t por 65,536 t clcl 2 notes for power cycle ti ming characteristics 1. startup time for crystals varies with load capacitanc e and manufacturer. time shown is for an 11.0592mhz crystal manufactured by fox crystal. 2. reset delay is a synchronous counter of crystal oscilla tions after crystal startup. counting begins when the level on the xtal1 input meets the v ih2 criteria. at 25mhz, this time is 2.62ms. program memory read cycle downloaded from: http:///
ds80c320/ds80c323 high-speed/low-power microcontrollers 31 of 38 data memory read cycle downloaded from: http:///
ds80c320/ds80c323 high-speed/low-power microcontrollers 32 of 38 data memory write cycle data memory write with stretch = 1 downloaded from: http:///
ds80c320/ds80c323 high-speed/low-power microcontrollers 33 of 38 data memory write with stretch = 2 4-cycle data memory write stretch value = 2 external clock drive downloaded from: http:///
ds80c320/ds80c323 high-speed/low-power microcontrollers 34 of 38 serial port mode 0 timing serial port 0 (synchronous mode) high speed operation sm2 = 1 txd clock = xtal/4 serial port 0 (synchronous mode) sm2 = 0 txd clock = xtal/12 downloaded from: http:///
ds80c320/ds80c323 high-speed/low-power microcontrollers 35 of 38 power-cycle timing downloaded from: http:///
ds80c320/ds80c323 high-speed/low-power microcontrollers 36 of 38 package information for the latest package outline information and land patterns, go to www.maxim-ic.com/packages . package type package code document no. 44 tqfp c44+2 21-0293 44 mqfp m44+10 21-0269 44 mqfp m44+5 21-0826 40 pdip p40+1 21-0044 44 plcc q44+1 21-0049 downloaded from: http:///
ds80c320/ds80c323 high-speed/low-power microcontrollers 37 of 38 data sheet revision summary the following represent the key differences between the 101006 and 070505 version of the ds80c320/ds80c323 data sheet. please review this summary carefully . 1. deleted ds80c323-mnd from ordering informati on table (page 2). device was never manufactured. the following represent the key differences between the 070505 and 051804 version of the ds80c320/ds80c323 data sheet. please review this summary carefully . 2. added pb-free/rohs-compliant part numbe rs to ordering information table. 3. deleted the a from the ipc/jedec j-std-020 specification in the absolute maximum ratings. the following represent the key differen ces between the 051804 and the 112299 version of the ds80c320/ds80c323 data sheet. please review this summary carefully . 1. removed preliminary status as a result of final characterization. 2. added industrial temperature ds80c323 devices to ordering information. 3. updated soldering temperature specifi cation to reflect jedec standards. 4. updated the following ds80c323 ac timing parameters with final characterization data: t lhll , t llax1 , t llax2 , t llax2 , t lliv , t llpl , t pliv , t aviv1 , t rldv , t rhdz , t lldv , t avdv1 , t avdv2 , t llwl , t avwl1 , t avwl2 , t qvwx , t whqx , t whlh . 5. updated the following ds80c320 ac timing para meters with final characterization data: t whqx , t lhll , t llax2 , tlldv, t avdv1 , t llwl , t avwl1 , t avwl2 . 6. added note advising the need to reset wa tchdog timer before setting the stop bit. 7. added note clarifying drive strength of p0, p2, ale, psen . 8. obsoleted ds80c320 25mhz ac timing tables ; merged into 33mhz ac timing tables. 9. corrected serial port mode 0 timing diag rams to show correct order of d6, d7. the following represent the key differences between the 041896 and the 052799 version of the ds80c320 data sheet. please review this summary carefully. 1. corrected v cc pin description to show ds80c323 operation at +3v. 2. corrected timed access descriptio n to show three-cycle window. 3. modified absolute maximum ratings for any pin relative to around, v cc relative to ground. 4. changed minimum oscillator frequency to 1mhz when using ex ternal crystal. 5. clarified that t por begins when xtal1 reaches v ih2 . the following represent the key differences between the 103196 and the 041896 version of the ds80c320 data sheet. please review this summary carefully. 1. updated ds80c320 25mhz ac characteristics. the following represent the key differences between the 041895 and the 031096 version of the ds80c320 data sheet. please review this summary carefully. 1. remove port 0, port 2 from v oh1 specification (pcn b60802). 2. v oh1 test specification clarified (rst = v cc ). 3. add t avwl2 marking to external memory read cycle figure. 4. correct tqfp drawing to read 44-pin tqfp. 5. rotate page 1 tqfp illustration to match assembly specifications. the following represent the key differences between the 031096 and the 052296 version of the ds80c320 data sheet. please review this summary carefully. 1. added data sheet revision summary section. the following represent the key differences between 05/23/96 and 05/22/96 version of the ds80c320 data sheet and between 05/23/96 and 03/27/95 version of the ds80c323 data sheet. please review this summary carefully. ds80c320: 1. add ds80c323 characteristics. 2. change ds80c320 v pfw specification from 4.5v to 4.55v (pcn e62802). 3. update ds80c320 33mhz ac characteristics. ds80c323: 1. delete data sheet. contents moved to ds80c320/ds80c323. downloaded from: http:///
ds80c320/ds80c323 high-speed/low-power microcontrollers 38 of 38 maxim/dallas semiconductor cannot assume res ponsibility for use of any circuitry other than circuitry entirely embodied in a ma xim/dallas semiconductor product. no circuit patent licenses are implied. maxi m/dallas semiconductor reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ? 2006 maxim integrated products the maxim logo is a registered trademark of maxim integrated products, inc. the dallas logo is a registered trademark of dallas semiconductor corporation. data sheet revision summary (continued) the following represent the key differen ces between the 05/22/96 and the 10/21/97 version of the ds80c320 data sheet. please review this summary carefully. ds80c320 1. added note to clarify i il specification. 2. added note to clarify ac timing conditions. 3. corrected erroneous t qvxl label on figure serial port mode 0 timing to read t qvxh . 4. added note to prevent accidental corruption of watc hdog timer count while ch anging counter length. ds80c323 1. added note to clarify i il specification. 2. remove port 2 from v oh1 specification, add port 3. 3. i oh for v oh3 specification changed from -3ma to -2ma. 4. added note to clarify ac timing conditions. downloaded from: http:///

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